summaryrefslogtreecommitdiff
path: root/Q1.core/Arch/Chip.cs
diff options
context:
space:
mode:
authorMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-18 06:50:43 +1000
committerMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-18 06:50:43 +1000
commit08ee9a129c81cc1cafcfe830b02b4f9c036334ca (patch)
tree6e4dcbeff96bbbbe65deff7312b416cd50ae69bf /Q1.core/Arch/Chip.cs
parentc528862deca86c606cead1c9d199ff22a6b4ac89 (diff)
add: Initial implementation of all instructions
Diffstat (limited to 'Q1.core/Arch/Chip.cs')
-rw-r--r--Q1.core/Arch/Chip.cs9
1 files changed, 9 insertions, 0 deletions
diff --git a/Q1.core/Arch/Chip.cs b/Q1.core/Arch/Chip.cs
index af131dd..69a0877 100644
--- a/Q1.core/Arch/Chip.cs
+++ b/Q1.core/Arch/Chip.cs
@@ -140,4 +140,13 @@ public class Chip
else throw new InvalidOperationException($"Invalid register index: {index}");
}
+ public void Interrupt(u16 code)
+ {
+ if (code >= ChipLayout.IVT_COUNT)
+ throw new InvalidOperationException($"Invalid interrupt code: {code}");
+
+ this.Push(this.Pc);
+ u16 interruptVectorAddress = (u16) (ChipLayout.IVT_START + code * 2);
+ this.Pc = this.Bus.ReadWord(interruptVectorAddress);
+ }
} \ No newline at end of file