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authorMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-18 07:19:22 +1000
committerMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-18 07:19:22 +1000
commit0bb62fc65526a0981cd328dea1b09aba8ce0a576 (patch)
treea601bb87ead0f58674ee18088e9e41e77512d3b8 /Q1.core/Components/Memory.cs
parent203331522e22c778ff830c3c6cf4f439778939fa (diff)
add: Add bus
Diffstat (limited to 'Q1.core/Components/Memory.cs')
-rw-r--r--Q1.core/Components/Memory.cs21
1 files changed, 21 insertions, 0 deletions
diff --git a/Q1.core/Components/Memory.cs b/Q1.core/Components/Memory.cs
new file mode 100644
index 0000000..9d23c7a
--- /dev/null
+++ b/Q1.core/Components/Memory.cs
@@ -0,0 +1,21 @@
+namespace Q1.core.Components;
+
+public class Memory : IAddressable
+{
+ private readonly u8[] _memory;
+
+ public u16 AddressableStart { get; }
+ public u16 AddressableEnd { get; }
+
+ public Memory(u16 start, u16 size)
+ {
+ this.AddressableStart = start;
+ this.AddressableEnd = (u16) (start + size);
+
+ this._memory = new u8[size];
+ }
+
+ public u8 Read(u16 address) => this._memory[address];
+ public void Write(u16 address, u8 value) => this._memory[address] = value;
+ public void Clock() { /* No timing behavior for simple memory */ }
+} \ No newline at end of file