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authorMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-20 06:04:13 +1000
committerMelodi <62381002+Melodi17@users.noreply.github.com>2026-03-20 06:04:13 +1000
commit571e44a12d2a52e92c1165ec294469d3d384faef (patch)
treed278303fe080322a7a4aeb122c09b6cc4bafaee7 /Q1.core/Components/Memory.cs
parent6f8356eca832e2350424b417cdea2d8d8eb6b1e3 (diff)
change: Split addressable and bus device
Diffstat (limited to 'Q1.core/Components/Memory.cs')
-rw-r--r--Q1.core/Components/Memory.cs4
1 files changed, 2 insertions, 2 deletions
diff --git a/Q1.core/Components/Memory.cs b/Q1.core/Components/Memory.cs
index 9d23c7a..38c33ee 100644
--- a/Q1.core/Components/Memory.cs
+++ b/Q1.core/Components/Memory.cs
@@ -1,6 +1,6 @@
namespace Q1.core.Components;
-public class Memory : IAddressable
+public class Memory : IBusDevice
{
private readonly u8[] _memory;
@@ -17,5 +17,5 @@ public class Memory : IAddressable
public u8 Read(u16 address) => this._memory[address];
public void Write(u16 address, u8 value) => this._memory[address] = value;
- public void Clock() { /* No timing behavior for simple memory */ }
+ public void Clock(Bus bus) { /* No timing behavior for simple memory */ }
} \ No newline at end of file